Method and apparatus of fault diagnosis for integrated logic circuits

ABSTRACT

In a method for diagnosing faults in an integrated logic circuit including a plurality of input signal lines, a plurality of output signal lines and a plurality of gates connected between the input signal lines and the output signal lines, different symbols are injected into fanout branches of one faulty candidate of the gates.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method and apparatus for carrying outfault diagnosis for integrated logic circuits (or “circuits” hereafter),to achieve high diagnostic resolution even in the presence of complex,dynamic, and/or multiple defects, all inevitable in deep-submicroncircuits.

2. Description of the Related Art

Failure analysis is the process of localizing physical defects in afailing circuit and identifying their root causes. Failure analysis isindispensable for silicon debugging, yield improvement, and reliabilityenhancement. The key part in the failure analysis is defectlocalization, which is achieved by first using a fault diagnosisprocedure to identify suspicious areas in a failing circuit and thenusing physical inspection means, such as an electron beam (EB) tester tosearch in the identified suspicious areas for actual defects.

Fault diagnosis is the process of identifying suspicious areas in afailing circuit by making use of logical faults assumed in a circuitmodel. A logical fault has two attributes: location and logicalbehavior. In a gate-level circuit model, the location attribute is oneor more nets or pins, and the logical behavior attribute is one or morelogic values. Fault modeling defines these attributes in a generalmanner. The process of identifying faults, with likely link to physicaldefects, is known as fault diagnosis. Physical defects can becharacterized from three aspects: complexity (simple or complex),temporality (static or dynamic), and cardinality (single or multiple). Asimple defect forces a single site to a fixed logic value of 0 or 1. Acomplex defect, such as a resistive short or open, causes multipleeffects around the defect site. For example, a complex defect in afanout gate forces its output to an intermediate voltage and multiplefaulty logic values may appear at its fanout branches depending on thethreshold voltages of the branches (see: D. Lavo, T. Larrabee, and B.Chess, “Beyond the Byzantine Generals: Unexpected Behavior and BridgingFault Diagnosis”, Proc. Intl. Test Conf., pp. 611-619, 1996). Such acomplex defect is called a Byzantine defect in this paper, A staticdefect shows the same behavior for all input vectors, while a dynamicdefect changes its behavior for different input vectors because thestrength of a signal can vary for different input conditions. Finally, acircuit may contain a single defect or multiple defects.

Based on this defect classification, the defect scenario of a failingcircuit can be trivial or non-trivial. The existence of a simple,static, and single defect is a trivial defect scenario, whereas theexistence of complex, dynamic, or multiple defects is a non-trivialdefect scenario.

In a trivial defect scenario, the failing circuit has exactly oneconstant defective effect at one location. Techniques based on thesingle stuck-at fault model, which assume a line to be fixed at a logicvalue of 0 or 1, can readily achieve accurate diagnosis for thisscenario.

In reality, a failing circuit is more likely to have a nontrivial defectscenario. In this case, the circuit either has defective effects atmultiple locations or the behavior of a defect changes for differentinput vectors. Obviously, the single stuck-at fault model cannotrepresent physical defects of this type, and accurate fault diagnosis isgenerally difficult to achieve.

The defect complexity issue in a non-trivial defect scenario has beenaddressed by using a combination of simple fault models or by using arealistic fault model. For example, a technique (see: S. Venkataramanand S. Drummonds, “POIROT: A Logic Fault Diagnosis Tool and ItsApplications”, Proc. Intl. Test Conf., pp. 253-262, 2000) uses fourfault models to cover various defects. On the other hand, variousrealistic fault models, such as stuck-open (see: S. Venkataraman and S.Drummonds, “POIROT. A Logic Fault Diagnosis Tool and Its Applications”,Proc. Intl. Test Conf., pp. 253-262, 2000), bridging (see: S. D.Millman, E. J. McCluskey, and J. M. Acken, Diagnosing CMOS BridgingFaults with Stuck-At Fault Dictionaries', Proc. Intl. Test Conf., pp.860-870, 1990; P. Maxwell and R. Aiken, “Biased Voting: A Method forSimulating CMOS Bridging Faults in the Presence of Variable Gate LogicThresholds”, Proc. Intl. Test Conf., pp. 63-72, 1993.), transistorleakage (W. Mao and R. K. Gulati, “QUIETEST: A Quiescent Current TestingMethodology for Detecting Short Faults”, Proc. ICCAD′ 90, pp. 280-283,November 1990), and Byzantine (see: D. Lavo, T. Larrabee, and B. Chess,“Beyond the Byzantine Generals: Unexpected Behavior and Bridging FaultDiagnosis”, Proc. Intl. Test Conf., pp. 611-619, 1996; S. Huang,“Speeding Up the Byzantine Fault Diagnosis Using Symbolic Simulation”,Proc. VLSI Test Symp., pp. 193-198, 2002), to better reflect actualdefect mechanisms.

The defect cardinality issue in a non-trivial defect scenario has beenaddressed (see: M. Abramovici and M. Breuer, Multiple Fault Diagnosis inCombinational Circuits Based on an Effect-Cause Analysis, IEEE Trans. onComp., vol. 29, no. 6, pp. 451-460, 1980; H. Cox and J. Rajski, “AMethod of Fault Analysis for Test Generation and Fault Diagnosis”, IEEETrans. On Computer-Aided Design, vol. 7, no. 7, pp. 813-833, 1988; H.Takahashi, K. O. Boateng, K. K Saluja, and Y. Takamatsu, “On DiagnosingMultiple Stuck-At Faults Using Multiple and Single Fault Simulation”,IEEE Trans. on Computer-Aided Design, vol. 21, no. 5, pp. 362-368,2002), all by targeting multiple tuck-at faults.

Recently, per-test fault diagnosis is gaining popularity in faultdiagnosis for a non-trivial defect scenario. Per-test means that failingvectors are processed one at a time. The basic idea is that only one ofthe multiple defects in a circuit may be activated by one failing vectorin some cases. As a result, a single fault model can be assumed for theactivated defect and a relatively easy fault diagnosis procedure basedon single fault simulation can be used for a non-trivial defectscenario. Thus, per-test fault diagnosis addresses both temporality andcardinality issues, and has been shown to be highly effective for anon-trivial defect scenario.

A prior art per-test method uses the single stuck-at fault model (see:T. Bartenstein, D. Heaberlin, L. Huisman, and D. Sliwinski, “DiagnosingCombinational Logic Designs Using the Single Location At-a-Time (SLAT)Paradigm” Proc. Intl. Test Conf., pp. 287-296, 2001). Like otherper-test fault diagnosis methods, this method is based on twoassumptions. The first assumption is that even when multiple defectsexist, the simulated output response of a circuit with an assumed singlefault may match the actual output response of the corresponding failingcircuit under a certain failing input vector. Such a failing inputvector is called a SLAT vector. The second assumption is that if thesimulated output response of a circuit with an assumed single faultmatches the actual output response under a SLAT vector, the possibilitythat the fault actually links to a physical defect is high. Theadvantage of the per-test fault diagnosis method is that a single faultmodel can be used in fault diagnosis for dynamic and multiple defects.

Several other per-test fault diagnosis methods have been proposed (see:S. Venkataraman and S. Drummonds, “POIROT: A Logic Fault Diagnosis Tooland Its Applications” Proc. Intl. Test Conf., pp. 263-262, 2000; J.Waicukauski and E. Lindbloom, “Failure Diagnosis of StructuredCircuits”, IEEE Design and Test of Comp., vol. 6, no. 4, pp. 49-60,1989; D. Lavo, I. Hartanto, and T. Larrabee, “Multiplets, Models and theSearch for Meaning”, Proc. Intl. Test Conf., pp. 250-259, 2002). Thesingle stuck-at fault model is used in the above-mentioned documents ofWaicukauski et al., Bartenstein et al. and Lavo et al., while acombination of stuck-at, stuck-open, net, and bridging faults is used inthe document of Venkataraman et al. These methods attempt to find aminimal set of faults that explains as many failing vectors as possible.Such a fault set is called a multiplet in the document of Bartenstein etal.

However, the diagnostic resolution or accuracy of the above-mentionedprior art per-test fault diagnosis method is often low for a circuitwith complex defects. The major reason is that the single stuck-at faultmodel cannot accurately represent the logic behaviors of complexdefects, such as Byzantine defects. In addition, a simple criterion isused for matching simulated output responses and actual outputresponses, which often results in diagnostic information loss, leadingto misdiagnosis. All these disadvantages contribute to significantlyincreased cost and time of failure analysis. As a result, there is astrong need to propose a new per-test fault method that can achieve highdiagnostic resolution even in the presence of complex, dynamic, andmultiple defects.

SUMMARY OF THE INVENTION

Accordingly, a primary object of this present invention is to provide amethod and apparatus of per-test fault diagnosis for complex, dynamic,and multiple defects in an integrated logic circuit to achieve highdiagnostic resolution.

The present invention is summarized as follows:

(a) X-Fault Model

The X-fault model is defined as follows:

A fanout-free gate has one X-fault, corresponding to any physical defector defects in the gate or on its output. The X-fault assumes a logicvalue at the output, which is opposite to the fault-free value at theoutput. Such an X-fault is called a fanout-free X-fault. On the otherhand, a fanout gate has one X-fault, corresponding to any physicaldefect or defects in the gate or on its fanout branches. The X-faultassumes different X symbols on the fanout branches of the gate torepresent unknown logic values in fault simulation. Such an X-fault iscalled a fanout X-fault.

The X-fault model has the following characteristics:

Generality: One single X-fault can represent all possible faulty logiccombinations at a defect site, while multiple stuck-at faults are neededto cover the same defect scenario.

Size: The number of X-faults in a circuit is manageable since it isequal to the number of gates in the circuit.

Accuracy: The X-fault model handles the unknown faulty behavior of acomplex defect such as a Byzantine defect with different X symbols. Nodiagnostic information is lost since no effort is made to aggressivelydetermine faulty logic values with an assumption, such as wired-AND,wired-OR, driving, etc., that may not be always true in reality.

Flexibility: The X-fault model allows a fault to have different faultybehaviors under different input vectors, making it suitable for theper-test fault diagnosis scheme in handling dynamic defects.

(b) New Matching Criterion

All previous per-test fault diagnosis methods use a strict matchingcriterion, in which a fault simulation result for a fault in a circuitmodel is compared with the corresponding observed response of the realcircuit at all primary outputs under a failing vector. This oftenresults in a mismatch, which leads to lower diagnostic resolution. Thepresent invention uses a relaxed matching criterion, in which comparisonis conducted at primary outputs that are structurally reachable from thefault. This can greatly improve diagnostic resolution. Note that primaryoutputs here include both conventional primary outputs and pseudoprimary outputs in a full-scan circuit.

(c) Diagnostic Information Extraction

All previous per-test fault diagnosis methods only use the matchinginformation as diagnostic information. In the present invention, inaddition to the matching information between a fault-simulation resultand its corresponding circuit response, the number of matched errors andthe depth of a fault are also taken into consideration to extract morediagnostic information. This can greatly improve diagnostic resolution.

(d) Diagnosis Value

In the present invention three factors, i.e. the matching information,the number of matched errors, and the depth of a fault, are all used inper-test fault diagnosis. A diagnosis value is calculated for each faultbased on the three factors. Generally, the diagnosis value for a faultunder a failing input vector is zero if the fault-simulation result andits corresponding circuit response does not match for the fault and thefailing input vector. If the fault-simulation result and itscorresponding circuit response match, the diagnosis value for the faultunder the failing input vector is a value greater than zero, and thevalue is calculated based on the number of matched errors and the depthof a fault.

(e) Diagnosis Table

The diagnosis values for all faults and all failing input vectors arestored in a diagnosis table. Note that each failing vector remaining inthe fault diagnosis table corresponds to at least one fault whosediagnosis value is not zero. From this table, the average diagnosisvalue for each fault under all failing input vectors are also calculatedand stored.

(f) Multiplet Scoring

As all previous per-test fault diagnosis methods, the present inventionalso finds multiplets as diagnosis results. Suppose that (Xij)m×n is afault diagnosis table, whose rows correspond to a set of m failingvectors and the columns to a set of n faults. A multiplet is a minimalset of faults {Fj1, Fj2, . . . , Fjh} such that any failing vector ti inthe table corresponds to at least one non-zero entry in {Xij1, Xij2, . .. , Xijh} for i=1, 2, . . . , m. Unlike all previous per-test faultdiagnosis methods, however, the present invention scores each multipletby the sum of the average diagnosis values of all faults in themultiplet. As a result, all multiplets are ordered by their scores.

The new techniques listed in above (a) through (f) greatly improves thecapability of per-test fault diagnosis, and makes it possible to achievehigh diagnostic resolution even when complex, dynamic, and multipledefects exists in a failing integrated logic circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, advantages and features of the inventionwill become more apparent when considered with the followingspecification and accompanying drawings wherein:

FIG. 1 is an example of a failing circuit with a defect in a gate;

FIG. 2 is a diagram for showing the possibility of multiple logicbehaviors of the defect of FIG. 1;

FIG. 3 is an example of the X-fault model, in accordance with thepresent invention;

FIG. 4A is an example of an integrated logic circuit;

FIG. 4B is a table showing the relationship between the input vectorsand the expected output responses of FIG. 4A;

FIG. 5 is a flowchart of the per-test fault diagnosis method, inaccordance with the present invention;

FIG. 6 is a detailed flowchart of the X-fault simulation step of FIG. 5,in accordance with the present invention;

FIG. 7 is a circuit diagram for explaining the X-injection step of FIG.6, in accordance with the present invention;

FIG. 8 is a circuit diagram for explaining the X-propagation step ofFIG. 6, in accordance with the present invention;

FIG. 9 is a circuit diagram for explaining the X-resolution step of FIG.6, in accordance with the present invention;

FIGS. 10A and 10 are circuit diagrams for explaining the reachableprimary outputs, in accordance with the present invention;

FIG. 11 is a detailed flowchart of the diagnosis value calculation stepof FIG. 6, in accordance with the present invention;

FIGS. 12A, 12B and 12C are diagrams for explaining the effective errorrate and the fault level of FIG. 11, in accordance with the presentinvention;

FIG. 13 is a circuit diagram for explaining the definition of the faultlevel of FIG. 11, in accordance with the present invention; and

FIG. 14 is an example fault diagnosis table, in accordance with thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

Generally, the fault diagnosis method requires high accuracy and highefficiency.

The “accuracy” is defined by a possibility that the faults to belocalized may be localized in the suspicious area. That is, when theaccuracy is low, the faults to be localized may not be localized in thesuspicious area, so that it is impossible to identify the root causes ofthe faults. On the other hand, when the accuracy is high, the faults tobe localized may be localized in the suspicious area, so that it isimpossible to identify the root causes of the faults. In other words,the maximum accuracy means that the faults to be localized are alwayslocalized in the suspicious area, thus identifying the root causes ofthe faults.

The “efficiency” is defined by the size of the suspicious area. That is,when the efficiency is low, the size of the suspicious area is large, sothat it may take a long time to localize the faults. On the other hand,when the efficiency is high, the size of the suspicious area is small,so that it may take a short time to localize the faults.

Physical defects can be generally characterized from three aspects:simple or complex complexity, static or dynamic temporality, and singleor multiple cardinality.

Regarding physical defects of a simple complexity, a static temporalityand a single cardinality, high accuracy and high efficiency can beeasily achieved by a fault diagnosis method of a single stuck-at-faultmodel assuming a line to be fixed at logic value “0” or “1”. On theother hand, regarding physical defects of a complex complexity, adynamic temporality or a multiple cardinality, since the singlestuck-at-fault model cannot represent such defects, an accurate faultdiagnosis method is generally difficult to achieve with high accuracyand high efficiency.

In the above-mentioned prior art per-test fault diagnosis method,however, as explained above, the accuracy is low for a circuit withcomplex defects, since a misdiagnosis may occur for a Byzantine defectsuch as a resistive short or open which shows a plurality of logicalbehaviors as illustrated in FIGS. 1 and 2. Note that FIG. 1 is a circuitdiagram for explaining a Byzantine defect, and FIG. 2 is a diagram forexplaining fault values of fanout signal lines of FIG. 1.

In FIG. 1, assume that the voltage at an output line L of a gate G ischanged by a Byzantine defect D between a ground voltage GND and a powersupply voltage VDD, and also, fanout signal lines L₁ and L₂ connected toan output line L of the gate G have threshold voltages V_(th1) andV_(th2), respectively (V_(th1)<V_(th2)). Note that the thresholdvoltages V_(th1) and V_(th2) are actually defined by those of thepost-stage input transistors (not shown) connected to the fanout signallines L₁ and L₂. In this case, as illustrated in FIG. 2B, the fanoutsignal lines L₁ and L₂ have three logic combinations (0, 0), (1, 0) and(1, 1) depending upon the output voltage V of the gate G as illustratedin FIG. 2, and the logic combinations (0, 0) and (1, 0) are possiblyfaulty. Therefore, it is impossible to know which one will show up dueto an unknown defect parameter such as a resistive short defectcharacterized by a Byzantine defect. This Byzantine defect can becomplex when the fanout signal lines L₁ and L₂ both have faulty logicvalue “0”.

In FIG. 3, which illustrates an example of the X-fault model, inaccordance with the present invention, X₁ and X₂ denote two arbitraryfaulty logic values. Obviously, <L₁=X₁, L₂=X₂> covers any possiblefaulty logic combination that may appear on L₁ and L₂ as shown inFIG. 1. Therefore, the fanout X-fault model can closely represent suchcomplex defects as Byzantine defects.

In FIG. 4A, which illustrates an example of an integrated logic circuitunit 1, this integrated logic circuit unit 1 is formed by gates G₁, G₂,G₃ and G₄, five input signal lines I₁, I₂, . . . , I₅ and three outputsignal-lines O₁, O₂ and O₃. In this case, if the integrated logiccircuit unit 1 is normally operated under the condition that an inputvector VEC is applied to the input signal lines I₁, I₂, . . . , I₅, anexpected output response EXO is obtained at the output signal lines O₁,O₂ and O₃. An example of the relationship between the input vector VECand the expected output response EXO is illustrated in FIG. 4B. Notethat, in FIG. 4A, an input vector VECi=(0, 1, 1, 0, 1) is applied as theinput vector VEC to the input signal lines I₁, I₂, . . . , I₅, and itsresulting expected output response EXO=(1, 0, 1) is obtained.

An example of the fault diagnosis method in accordance with the presentinvention will be explained below.

FIG. 5 is a main routine.

First, at step 501, an input vector VEC is initialized to VEC1, i.e.,i=1.

Next, at step 502, a failing candidate gate G_(i) is initialized to G₁,j=1.

Next, at step 503, diagnosis information collection is carried out.

This diagnosis information collection step 503 will be explained indetail next with reference to FIG. 6.

First, at step 601, it is determined whether or not the gate G_(i) hasfanout branches. As a result, only if there are such fanout branches,does the control proceed to steps 602 through 604. Otherwise, thecontrol proceeds to steps 605 and 606.

For example, in FIG. 4A, the gates G₁ and G₂ have fanout branches, whilethe gates G₃, G₄ and G₅ have no fanout branches.

At step 602, X-injection is carried out to assign different X symbolsfor showing uncertain faulty values in the calculation of simulatedoutput responses to the fanout branches of the gate X_(i). For example,as illustrated in FIG. 7, if the gate G₁ is a failing candidate gatehaving fanout branches b₁, b₂ and b₃, X₁(b₁), X₂ (b₂) and X₃(b₃) areinjected into the fanout branches b₁, b₂ and b₃, respectively. Here, oneX symbol consists of three parts: a letter X, a subscript to distinguishamong different X symbols, a plurality of fanout branch names inparenthesis. The different X symbols represent a combination of logicvalues for showing a complex defect such as a Byzantine defect.

Next, at step 603, X-propagation is carried out-t-o calculate an initialsimulated output response ISO. That is, the X symbols injected by theX-injection step 602 are propagated by applying an input vector VEC tothe input signal lines I₁, I₂, . . . , I₅ under the followingconditions:

1) Inverted information should be preserved. That is, a gate having aninverting function preserves inverted information such as /X_(i)(b). Inother words, an inversion of an X symbol is allowed to suppress thegeneration of new X symbols, so that the number of output signal linesto which the X symbols reach can be effectively decreased. As a result,the power consumption required for X-propagation can be decreased. Forexample,

AND (X_(i)(b), /X_(i)(b))=0

OR (X_(i)(b), /X_(i)(b))=1

NAND (/X_(i)(b₁, b₂), 1)=X_(i)(b₁, b₂)

OR (X_(i)(b₁), /X_(i)(b₁), 0, X₂(b₂))=1

2) Branches should be reserved. That is, only when the output signal ofa gate which receives X symbols such as X₁(b₁), X₂(b₂), . . . ,X_(h)(b_(h)) or their compliments is none of 0, 1, X and /X, is a new Xsymbol having a new subscript generated at the output of this gate. Forexample,

NOR (X₃(b₁, b₂), X₂(b₂), X₄(b₃))=X₅(b₁, b₂, b₃)

AND (/X₁(b₁), X₃(b₃))=X₆(b₁,b₃)

An initial simulated output response ISO depends upon an input vectorVEC and a gate G_(i), i.e., a function (VEC, G_(i)). For example, inFIG. 8,

ISO (VECi, G₁)=(/X₁(b₁), X₄(b₁, b₂), 1)

Next, at step 604, X-resolution, i.e., binary logic simulations arecarried out by assigning 0 or 1 to the injected X symbols, thus removingthe ambiguity. If the injected X symbols are defined by X₁(b₁), X₂(b₂),. . . , X_(h)(b_(h)), the set B of responsible fanout branches is b₁∩b₂∩. . . ∩b_(h). Therefore, 2^(h) runs of binary logic simulations cansolve all the X symbols. However, if the threshold voltages of thefanout branches b₁, b₂, . . . , b_(h) are already known, only (h+1) runsof binary logic simulations can solve all the X symbols. Also, since noconsideration is given to the fanout branches not included in areachable output response RCO which will be explained later, the numberof runs of binary logic simulations can be further decreased.

In FIG. 9, since the fanout branches b₁ and b₂ of the gate G₁ reach theoutput signal lines O₁ and O₂ as illustrated in FIG. 8, no considerationis given to the fanout branch b₃. Therefore, the 4 (=2²) failingcombinations of the fanout branches b₁, b₂ and b₃ are (0, 0, X), (1, 0,X), (0, 1, X) and (1, 1, X), so that their simulated output responsesSMO may be (1, 0, 1), (0, 0, 1), (1, 1, 1) and (0, 0, 1); however, thesimulated output response SMO=(1, 0, 1) is excluded due to the expectedoutput response EPO=(1, 0, 1). Thus, simulated output responses SMO bythe X-resolution are P₁=(0, 0, 1), P₂=(1, 1, 1) and P₃=(0, 0, 1).

Thus, one or more simulated output responses are obtained for eachcombination of one input vector and one faulty gate, which would relax amatching condition which will be explained later.

On the other hand, at step 605, an inverted logic value of a normallogic value is injected into the output line of a faulty gate G_(i). Forexample, an inverted logic value 0 is injected into the output signalline of a faulty gate which has a logic value 1 when this gate isnormal. This inverted logic value is clearly a failing logic value.

Next, at step 606, a conventional single stuck-at-fault simulation iscarried out.

Note that the operations at steps 605 and 606 have no directrelationship to the present invention, and therefore, no detaileddescription would be necessary for steps 605 and 606.

At step 607, a reachable output response RCO of the output signal linesO₁ and O₂ and O₃, which the output signal of an X faulty gate X_(i) canreach, is calculated. The reachable output response RCO depends upon theX faulty gate X_(i). For example, as illustrated in FIG. 10A, the outputsignal of the faulty gate G_(i) can reach the output signal line O₁through the gates G₂ and G₃, the output signal line O₂ through the gatesG₂ and G₄ and the output signal line O₃ through the gate G₅. Therefore,a reachable output response RCO=(1, 1, 1) is obtained. Similarly, asillustrated in FIG. 10B, the output signal of the faulty gate G₂ canreach the output signal line O₁ through the gate G₃ and the outputsignal line O₂ through the gate G₄. Therefore, a reachable outputresponse RCO=(1, 1, 0) is obtained.

Then, the control returns to step 504 of FIG. 5.

At step 504 of FIG. 5, a fault diagnosis is carried out in accordancewith the actual operation of the integrated logic circuit unit 1.

The fault diagnosis step 504 is illustrated in detail in FIG. 11. InFIG. 11, note that a gate G_(i) is assumed to have a plurality of fanoutbranches. If a gate G_(i) has no fanout branches, since the prior artsingle stuck-at-fault simulation is performed upon such a gate G_(i),the present invention has no relationship to such a gate G_(i).

First, at step 1101, a difference vector DEP is calculated by anexclusive OR operation between the bits of an observed output responseOBO at the output signal lines O₁, O₂ and O₃ of the integrated logiccircuit unit 1 and the corresponding bits of its expected outputresponse EXO.

Next, at step 1102, it is determined whether |DEF| is 0. As a result,when |DEF| is 0, this means that the observed output response OBOcoincides with the expected-output response EPO, i.e., no fault isgenerated, so that the control proceeds directly to step 505 of FIG. 5.On the other hand, when |DEF| is not 0, this means that the observedoutput response OBO does not coincide with the expected output responseEPO, i.e., a fault may be generated, so that the control proceeds tostep 1103.

At step 1103, the input vector VEC is replaced by a failing input vectorFVEC, i.e.,

FVEC←VEC

Steps 1104 to 1110 perform a matching operation between theabove-mentioned simulated output response SHO (P_(k)) and the observedoutput response OBO to obtain fault diagnosis values p(FVEC, G_(i)). Inthis case, since the fault diagnosis values p(FVEC, G_(i)) arecalculated in consideration of an error rate and a fault level, each ofthe fault diagnosis values p(FVEC, G_(i)) varies from 0 to 1. Note thatthe fault diagnosis values (matching values) of the prior art per-testfault diagnosis method were 1 (coincidence) or 0 (incoincidence).

Steps 1104 to 1110 are explained in detail below.

At step 1104, a value j for indicating a simulated output response P_(j)is initialized at 1. Here, assume that simulated output responses P₁,P₂, . . . , P_(k) (k≧1) are defined for a failing test input vector FVECand a failing gate G_(i).

Next, at 1105, a narrow sense matching operation is carried out. Thatis, it is determined whether or not the simulated output response P_(j)coincides with the observed output response OBO. As a result, when thesimulated output response P_(j) coincides with the observed outputresponse OBO, the control proceeds to step 1106. On the other hand, whenthe simulated output response P_(j) does not coincide with the observedoutput response OBO, the control proceeds to step 1107.

At step 1106, a fault diagnosis value p(FVEC, G_(i), j) as a matchingvalue is calculated byp(FVEC,G₁,j)←(L(G_(i))/L_(max))·(DEF∩RCO)/|RCO|

where (DEF∩RCO)/|RCO| defines an effective error rate, andL(G_(i))/L_(max) defines a fault level.

For example, as illustrated in FIG. 12A, for a failing input vectorFVEC1 and a faulty gate G₁, the number of errors is 3 and the effectiveerror rate is 100% (=3 errors/3 target errors). Also, as illustrated inFIG. 12B, for a failing input vector FVEC2 and a faulty gate G₂, thenumber of errors is 3 and the effective error rate is 33% (=1 errors/3target errors). Further, as illustrated in FIG. 12C, for a failing inputvector FVEC3 and a faulty gate G₃, the number of errors is 1 and theeffective error rate is 50% (=1 errors/2 target errors).

In FIGS. 12A, 12B and 12C, the faulty gate G₁ is far from the outputsignal lines O₁, O₂, . . . , O₅ than the gates G₂ and G₃. Intuitively,faults in the faulty gate G₁ hardly appear at the output signal linesO₁, O₂, . . . , O₅ as compared with those in the faulty gates G₂ and G₃.To compensate for this, a fault level L depending upon the substantialdistance between the faulty gate G_(i) and the output signal lines O₁,O₂, . . . is adopted. The fault level L is defined as follows:

1) The fault level at the output signal lines O₁, O₂, . . . is L=1.

2) If the fault level of an output of one gate is defined by L, thefault level of the input of this gate is defined by L+1.

3) If a gate has a plurality of fanout branches whose fault levels aredefined by L₁, L₂, . . . , the fault level of the stem output of thisgate is defined by a maximum level of the fault levels L₁, L₂, . . . .

4) L_(max) is defined by a maximum fault level within the integratedlogic circuit unit 1.

For example, as illustrated in FIG. 13, the fanout branches of thefaulty gate G₁ have fault levels L=2 and L=3, and therefore, the stemoutput of the faulty gate G₁ has a fault level L=3 which is the maximumlevel of L=2 and L=3.

On the other hand, at step 1107, a fault diagnosis value p(FVEC, G_(i),j) is made 0.

Steps 1108 and 1109 repeat the flow of steps 1105 to 1107 by the numberk of the simulated output response P_(j).

At step 1110, an average value p(FVEC, G_(i)) of the fault diagnosisvalues p(FVEC, G_(i), j) is calculated. This average value p(FVEC,G_(i)) is a final fault diagnosis value.

Then, the control returns to step 505 of FIG. 5.

Steps 505 and 506 repeat the flow composed of the information collectingstep 503 and the fault diagnosis step 504 by the number of faultcandidate gates. That is, step 505 determines whether or not there is afaulty gate left as a faulty candidate gate. Only when there is such afaulty gate, does the control proceed to step 506 which updates G_(i),and returns to step 503.

Steps 507 and 508 repeat the flow composed of steps 502 through 506 bythe number of input vectors. That is, step 507 determines whether or notthe input vector VECi is VECm. Only when VECi=VECm, does the controlproceed to step 508 which updates VECi and returns to step 502.

At step 509, a fault diagnosis table composed of final fault diagnosisvalues p(FVEC, G_(i)) as illustrated in FIG. 14 is generated. Note thatan average value for each G_(i) is calculated byΣp(FVEC,G_(i))/m

where m is the number of failing input responses.

For example, in FIG. 9,

L(G₁)=4

L_(max)=4

If an observed output response OBO is (0, 0, 1), then

P₁=OBO

P₂≠OBO

P₃=OBO

Therefore,

p(FVEC, G₁, 1)= 3/3·⅓=0.33

p(FVEC, G₁, 2)=0

p(FVEC, G₁, 3)= 3/3·⅓=0.33

As a result, $\begin{matrix}{{p\left( {{FVEC},G_{1}} \right)} = {\left( {0.33 + 0 + 0.33} \right)/3}} \\{= 0.22}\end{matrix}$

Next, at step 510, a multiplet is generated. Note that a multiplet is aminimum set of faults such that any failing input vector can beexplained by at least one fault in the minimum set.

A multiplet is composed of minimum covers and essential faults.

That is, all essential faults are extracted and excluded from the faultdiagnosis table to change it to a target diagnosis table. Note that oneessential fault is defined by a fault such that an entry in the faultdiagnosis table is the only non-zero entry in the corresponding row(failing input vector) and the corresponding column (faulty gate). Theessential faults are indispensable in the multiplet. If there is noessential fault, the target diagnosis table is the same as the originaldiagnosis table.

In FIG. 14, the faulty gate G₅ is an essential fault. Therefore, thefaulty gate G₅ is excluded from the original fault diagnosis table.

Then, minimal covers are extracted from the fault diagnosis table. Notethat one cover is defined by a set of faults such that any failing inputvector corresponds to at least one non-zero entry. There may be multiplecovers of different sizes. The covers of the smallest size are calledminimal covers.

In order to extract the minimal covers, a fault incompatibility graph isformed against the diagnosis table.

A fault compatibility graph can be easily derived from the faultincompatibility graph, since the two graphs are complementary to eachother.

Cover candidates are a set of faults showing 8 complete subgraphs:

{G₁}, {G₂}, {G₃}, {G₄},

{G₁, G₃}, {G₁, G₄}, {G₂, G₃}, {G₂, G₄}

Detected from the 8 complete subgraphs are covers;

{G₁, G₃}, {G₁, G₄}, {G₂, G₃}, {G₂, G₄}

Since all these covers have the same size, the covers are minimalcovers.

Next, at step 510, multiplets are generated by adding the essentialfault G₅ to the minimal covers:

{G₁, G₃, G₅}, {G₁, G₄, G₅}, {G₂, G₃, G₅}, {G₂, G₄, G₅}

Next, at step 511, scores of the multiplets are calculated to indicatethe top diagnosis result. That is,

{G₁, G₃, G₅}=0.27+0.36+0.14=0.77

{G₁, G₄, G₅}=0.27+0.04+0.14=0.45

{G₂, G₃, G₆}=0.16+0.36+0.14=0.66

{G₂, G₄, G₅}=0.16+0.04+0.14=0.34

As a result, {G₁, G₃, G₅} is the top diagnosis result.

Then, the routine of FIG. 5 is completed by step 512.

According to the inventors' experiments, in the prior art per-testdiagnosis method, the average value of multiplets was large and theaverage first hit location of the top diagnosis generating multipletswas low. On the other hand, according to the per-test diagnosis methodof the present invention, the average value of multiplets was small andthe average first hit location of the top diagnosis generatingmultiplets was high, i.e., almost first rank, at worst third rank.

Note that the above-mentioned flowcharts of FIGS. 5, 6 and 11 can bestored in an ROM or another nonvolatile memory or in a random accessmemory or another volatile memory.

As explained hereinabove, according to the present invention, highdiagnostic resolution can be obtained.

1. A method for modeling physical defects in an integrated logic circuitincluding a plurality of input lines, a plurality of output lines, and aplurality of logic gates connected between said input lines and saidoutput lines, comprising: using a fanout-free X-fault model for eachfanout-free gate of said logic gates, corresponding to any physicaldefect or defects in said fanout-free gate or on its output, for which alogic value at the output of said fanout-free gate, which is opposite toa fault-free value at the output of said fanout-free gate, is assumed;using a fanout X-fault model for each fanout gate of said logic gates,corresponding to any physical defect or defects in said fanout gate oron its fanout branches, for which different X symbols are assumed on thefanout branches of said fanout gate to represent unknown logic values;and calling fanout-free X-faults of said fanout-free X-fault model andfanout X-faults of said fanout X-fault model collectively as X-faults.2. The method as set forth in claim 1, further comprising: carrying outX-injection to assign different X symbols to the fanout branches of saidfanout gate to which a fanout X-fault is assumed; carrying outX-propagation to propagate said X symbols to said output lines; andcarrying out X-resolution to resolve all X symbols at outputs to obtaina final simulation result.
 3. The method as set forth in claim 2,wherein said X-injection carrying-out comprises assigning different Xsymbols to all fanout branches of said fanout gate to which said X-faultis assumed, wherein each of said X symbols has a form of Xi(bj) where iis a subscript to distinguish said X symbols from each other and bj is aset containing a name of one of said fanout branches to which one ofsaid X symbols is assigned.
 4. The method as set forth in claim 2,wherein said X-propagation carrying-out comprises applying a first rulein simulation to preserve inversion information, wherein inversion ofone X symbol is represented by its complement, the logic result ofcarrying out an AND operation on said X symbol and its complement Xsymbol is logic 0, and the logic result of carrying out an OR operationon said X symbol and its complement X symbol is logic
 1. 5. The methodas set forth in claim 2, wherein said X-propagation carrying-outcomprises applying a second rule in simulation to preserve branchinformation, wherein, if the result of a logic function for X symbols,Xi1(b1), Xi2(b2), . . . , Xih(bh), or their complements, is neitherlogic 0 nor logic 1, then a new X symbol, Xj(b1∪b2∪ . . . ∪bh) is usedto represent the result of said logic function, where ∪ represents a setunion operation and j is a new subscript that has not been used by otherX symbols yet.
 6. The method as set forth in claim 2, wherein saidX-resolution carrying-out comprises carrying out 2-valued logicsimulation if said outputs have X symbols after said X-propagation iscarried out for one of said fanout X-faults, wherein if said outputshave Xi1(b1), Xi2(b2), . . . , Xih(bh), or their complements, all logiccombinations for branches b1∪b2∪ . . . ∪bh, except the combinationcorresponding to the fault-free circuit, are assigned to the branches ofthe one of said fanout gates and simulated by 2-valued simulation one byone to obtain a set of simulated responses for said fanout X-fault.
 7. Amethod for fault diagnosis in an integrated logic circuit including aplurality of input lines, a plurality of output lines, and a pluralityof logic gates connected between said input lines and said output lines,said method comprising: collecting diagnostic information; calculating adiagnosis value in accordance with said diagnostic information;generating a fault diagnosis table in accordance with said diagnosisvalue; generating multiplets in accordance with said fault diagnosistable; and scoring said multiplets.
 8. The method as set forth in claim7, wherein said diagnostic information collecting comprises carrying outfault simulation for each fault under each failing input vector toobtained all simulated responses P1, P2, . . . , Pn, for said faultunder said failing input vector, wherein Pi (i=1, 2, . . . , n)=1 if Pimatches the observed response at said output lines that are structurallyreachable from one of said logic gates where said fault is assumed andPi (i=1, 2, . . . , n)=0 if Pi does not match the observed response atsaid output lines that are structurally reachable from the one of saidlogic gates where said fanout X-fault is assumed.
 9. The method as setforth in claim 2, wherein said diagnosis value calculating comprisescalculating a fault diagnosis value for a fault and a failing inputvector by (L(f)/_(max))·|DEF∩RCO|/|RCO|·((P1+P2+ . . . +Pn)/n), where fis said fault, L(f) is a fault level of said fault, L_(max) is themaximum fault level within said integrated logic circuit, DEF is a setof said output lines with errors under said failing input vector, RCO isa set of said output lines that are structurally reachable from one ofsaid gates where said fault is assumed, n is the total number ofsimulated response for said fault under said failing input vector, Pi(i=1, 2, . . . , n) is an i-th simulated response for said fault undersaid failing input vector, wherein Pi (i=1, 2, . . . , n)=1 if pimatches the observed response at output lines that are structurallyreachable from the one of said gates where said fault is assumed and Pi(i=1, 2, . . . , n)=0 if Pi does not match the observed response at saidoutput lines that are structurally reachable from the one of said gateswhere said fanout X-fault is assumed.
 10. The method as set forth inclaim 9, wherein said fault level calculating comprises using thefollowing conditions: (a) the fault level of each of said output linesis L=1; (b) the fault level of all input lines of a gate is L+1 if thefault level of the output line of said gate is L; and (c) the faultlevel of a stem line is the maximum value among L₁, L₂, . . . , Lm ifthe fault levels of all fanout branches from said stem are L₁, L₂, . . ., Lm.
 11. The method as set forth in claim 7, wherein said faultdiagnosis table generating comprises storing a diagnosis value for eachfault and each failing input vector in a two-dimensional table,(Xij)m×n, whose rows correspond to a set of m failing input vectors andthe columns to a set of n faults.
 12. The method as set forth in claim7, wherein said multiplet generating comprises finding all or a numberof multiplets from a fault diagnosis table, said multiplet being aminimal set of faults {Fj1, Fj2, . . . , Fjh} such that any failingvector ti in said fault diagnosis table corresponds to at least onenon-zero entry in {Xij1, Xij2, . . . , Xijh} for i=1, 2, . . . , m,wherein (Xij)m×n is said fault diagnosis table whose rows correspond toa set of m failing input vectors and the columns to a set of n faults.13. The method as set forth in claim 7, wherein said multiplet scoringcomprises calculating the score of each obtained multiplet, said scoreof said multiplet being a sum of average diagnosis values for all faultsin said multiplet, where the average diagnosis value of a fault is theaverage value of all diagnosis values of said fault for all failinginput vectors.
 14. A method for modeling physical defects in anintegrated logic circuit by an X-fault model, said X-fault modelcomprising: a fanout-free X-fault model for each fanout-free gate,corresponding to any physical defect or defects in said fanout-free gateor on its output, for which a logic value at the output of saidfanout-free gate, which is opposite to the fault-free value at theoutput of said gate, is assumed; and a fanout X-fault model for eachfanout gate, corresponding to any physical defect or defects in saidfanout gate or on its fanout branches, for which different X symbols areassumed on the fanout branches of said fanout gate to represent unknownlogic values.
 15. A method for carrying out fault simulation for afanout X-fault of a fanout gate, said method comprising: X-injecting toassign different X symbols to the fanout branches of said fanout gate;X-propagating to propagate the X symbols to outputs; and X-resolving toresolve all X symbols at outputs to obtain a final simulation result.16. The method as set forth in claim 15, wherein said X-injectingcomprises assigning different X symbols to all the fanout branches ofsaid fanout gate, each of said X symbols having the form of Xi(bi) wherei is a subscript to distinguish said X symbol from all other X symbolsand bi is a set containing names of said fanout branches to which one ofsaid X symbols is assigned.
 17. The method as set forth in claim 15,wherein said X-propagating comprises applying a first rule in simulationto preserve inversion information, wherein the inversion of an X symbolis represented by its complement, the logic result of performing an ANDoperation on an X symbol and its complement X symbol is logic 0, and thelogic result of performing an OR operation on an X symbol and itscomplement X symbol is logic
 1. 18. The method as set forth in claim 15,wherein said X-propagating comprises applying a second rule insimulation to preserve branch information, wherein, if the result of alogic function for X symbols, Xi1(b1), Xi2(b2), . . . , Xih(bh), ortheir complements, is neither logic 0 nor logic 1, then a new X symbol,Xj(b1∪b2∪ . . . ∪bh) is used to represent the result, where ∪ representsa set union operation and j is a new subscript that has not been usedyet.
 19. The method as set forth in claim 15, wherein said X-resolvingcomprises carrying out 2-valued logic simulation if outputs have Xsymbols after X-propagation is done, wherein if outputs of saidintegrated logic circuit have Xi1(b1), Xi2(b2), . . . , Xih(bh), ortheir complements, all logic combinations for branches b1∪b2∪ . . . ∪bhare assigned to said fanout branches and simulated by 2-valuedsimulation one by one.
 20. A method for carrying out fault simulation inan integrated logic circuit including a plurality of input signal lines,a plurality of output signal lines, and a plurality of gates connectedbetween said input signal lines and said output signal lines,comprising: injecting different symbols into fanout branches of one ofsaid gates in accordance with circuit information of said integratedlogic circuit; simulating said integrated logic circuit by applying aninput vector to the input signal lines of said integrated logic circuitto obtain one or more simulated output responses at the output signallines of said integrated logic circuit in accordance with the circuitinformation of said integrated logic circuit, after said differentsymbols are injected; and identifying a suspicious region of saidintegrated logic circuit where faults are expected to be localized, bycomparing an observed output response obtained at the output signallines of said integrated logic circuit while applying said input vectorto the input signal lines of said integrated logic circuit with saidsimulated output responses.
 21. The method as set forth in claim 20,wherein said simulating comprises propagating said symbols with numberinformation of said fanout branches to the output signal lines of saidintegrated logic circuit while said input vector is applied to the inputsignal lines of said integrated logic circuit, thus obtaining an initialsimulated output response at the output signal lines of said integratedlogic circuit.
 22. The method as set forth in claim 20, furthercomprising calculating a reachable output response from a faultycandidate gate to the output signal lines of said integrated logiccircuit in accordance with the circuit information of said integratedlogic circuit, said identifying comprising: comparing said observedoutput response with an expected output response while said input vectoris applied; comparing said observed output response with said simulatedoutput responses while said input vector is applied, only when saidobserved output response does not coincide with said expected outputresponse; calculating a first matching value in accordance with aneffective error rate of said observed output response and said expectedoutput response within said reachable output response and a fault leveldepending upon a substantial distance between said fault candidate gateand the output signal lines of said integrated logic circuit, when oneof said simulated output responses coincides with said observed outputresponse; calculating a second matching value of 0, when one of saidsimulated output responses does not coincide with said observed outputresponse; and calculating a third matching value of an average value ofsaid first and second matching values per one of said simulated outputresponses.
 23. The method as set forth in claim 22, wherein said firstmatching value is calculated byp(FVEC,G _(i) ,j)=(L(G _(i))/L _(max))·(DEF∩RCO)/|RCO| where FVEC issaid input; vector, G_(i) is said fault candidate gate, j is the numberof one of said simulated output responses, RCO is said reachable outputresponse, L(G_(i)) is said fault level under the conditions: 1) thefault level of the output signal lines is L=1, 2) if the fault level ofthe output of a gate is L, the fault level of its input is L+1, and 3)if the fault levels of the fanout signal lines of a gate are L₁, L₂, . .. , the fault level of their stem output is the maximum value of L₁, L₂,. . . , and L_(max) is the maximal fault level within said integratedlogic circuit.
 24. The method as set forth in claim 22, wherein saididentifying further comprises: generating a fault diagnosis table formedby said third matching value in the row of said input vector and in thecolumn of said fault candidate gate; renewing said fault diagnosis tableby excluding one or more essential faults from said fault diagnosistable when said essential faults are present therein, each of saidessential faults being a fault such that an entry in said faultdiagnosis table is the only non-zero entry in the corresponding row andthe corresponding column; extracting minimal covers from said faultdiagnosis table, each of said covers being defined by a set of faultssuch that any failing input vector corresponds to at least one non-zeroentry; and generating multiplets by adding said essential faults to saidminimal covers when there are said essential faults in said faultdiagnosis table, said multiplets being the same as said minimal coverswhen there are no essential faults in said fault diagnosis table. 25.The method as claim 24, wherein said identifying comprises scoring saidmultiplets using average fault diagnosis values per candidate gate. 26.A computer program for modeling physical defects in an integrated logiccircuit including a plurality of input lines, a plurality of outputlines, and a plurality of logic gates connected between said input linesand said output lines, comprising: a computer readable program code forusing a fanout-free X-fault model for each fanout-free gate of saidlogic gates, corresponding to any physical defect or defects in saidfanout-free gate or on its output, for which a logic value at the outputof said fanout-free gate, which is opposite to a fault-free value at theoutput of said fanout-free gate, is assumed; a computer readable programcode for using a fanout X-fault model for each fanout gate of said logicgates, corresponding to any physical defect or defects in said fanoutgate or on its fanout branches, for which different X symbols areassumed on the fanout branches of said fanout gate to represent unknownlogic values; and a computer readable program code for callingfanout-free X-faults of said fanout-free X-fault model and fanoutX-faults of said fanout X-fault model collectively as X-faults.
 27. Thecomputer program as set forth in claim 26, further comprising: acomputer readable program code for carrying out X-injection to assigndifferent X symbols to the fanout branches of said fanout gate to whicha fanout X-fault is assumed; a computer readable program code forcarrying out X-propagation to propagate said X symbols to said outputlines; and a computer readable program code for carrying outX-resolution to resolve all X symbols at outputs to obtain a finalsimulation result.
 28. The computer program as set forth in claim 27,wherein said X-injection carrying-out computer readable program codecomprises a computer readable program code for assigning different Xsymbols to all fanout branches of said fanout gate to which said X-faultis assumed, wherein each of said X symbols has a form of Xi(bj) where iis a subscript to distinguish said X symbols from each other and bj is aset containing a name of one of said fanout branches to which one ofsaid X symbols is assigned.
 29. The computer program as set forth inclaim 27, wherein said X-propagation carrying-out computer readableprogram code comprises a computer readable program code for applying afirst rule in simulation to preserve inversion information, whereininversion of one X symbol is represented by its complement, the logicresult of carrying out an AND operation on said X symbol and itscomplement X symbol is logic 0, and the logic result of carrying out anOR operation on said X symbol and its complement X symbol is logic 1.30. The computer program as set forth in claim 27, wherein X-propagationcarrying-out computer readable program code comprises a computerreadable program code for applying a second rule in simulation topreserve branch information, wherein, if the result of a logic functionfor X symbols, Xi1(b1), Xi2(b2), . . . , Xih(bh), or their complements,is neither logic 0 nor logic 1, then a new X symbol, Xj(b1∪b2∪ . . .∪bh) is used to represent the result of said logic function, where ∪represents a set union operation and j is a new subscript that has notbeen used by other X symbols yet.
 31. The computer program as set forthin claim 27, wherein said X-resolution carrying-out computer readableprogram code comprises a computer readable program code for carrying out2-valued logic simulation if said outputs have X symbols after saidX-propagation is carried out for one of said fanout X-faults, wherein ifsaid outputs have Xi1(b1), Xi2(b2), . . . , Xih(bh), or theirXXXcompliment complements, all logic combinations for branches b1∪b2∪ .. . ∪bh, except the combination corresponding to the fault-free circuit,are assigned to the branches of the one of said fanout gates andsimulated by 2-valued simulation one by one to obtain a set of simulatedresponses for said fanout X-fault.
 32. A computer program for faultdiagnosis in an integrated logic circuit including a plurality of inputlines, a plurality of output lines, and a plurality of logic gatesconnected between said input lines and said output lines, comprising: acomputer readable program code for collecting diagnostic information; acomputer readable program code for calculating a diagnosis value inaccordance with said diagnostic information; a computer readable programcode for generating a fault diagnosis table in accordance with saiddiagnosis value; a computer readable program code for generatingmultiplets in accordance with said fault diagnosis table; and a computerreadable program code for scoring said multiplets.
 33. The computerprogram as set forth in claim 32, wherein said diagnostic informationcollecting computer readable program code comprises a computer readableprogram code for carrying out fault simulation for each fault under eachfailing input vector to obtained all simulated responses P1, P2, . . . ,Pn, for said fault under said failing input vector, wherein Pi (i=1, 2,. . . , n)=1 if Pi matches the observed response at said output linesthat are structurally reachable from one of said logic gates where saidfault is assumed and Pi (i=1, 2, . . . , n)=0 if Pi does not match theobserved response at said output lines that are structurally reachablefrom the one of said logic gates where said fanout X-fault is assumed.34. The computer program as set forth in claim 32, wherein saiddiagnosis value calculating computer readable program code comprises acomputer readable program code for calculating a fault diagnosis valuefor a fault and a failing input vector by(L(f)/L_(max))·|DEF∩RCO|/|RCO|·((P1+P2+ . . . +Pn)/n), where f is saidfault, L(f) is a fault level of said fault, L_(max) is the maximum faultlevel within said integrated logic circuit, DEF is a set of said outputlines with errors under said failing input vector, RCO is a set of saidoutput lines that are structurally reachable from one of said gateswhere said fault is assumed, n is the total number of simulated responsefor said fault under said failing input vector, Pi (i=1, 2, . . . , n)is an i-th simulated response for said fault under said failing inputvector, wherein Pi (i=1, 2, . . . , n)=1 if pi matches the observedresponse at output lines that are structurally reachable from the one ofsaid gates where said fault is assumed and Pi (i=1, 2, . . . , n)=0 ifPi does not match the observed response at said output lines that arestructurally reachable from the one of said gates where said fanoutX-fault is assumed.
 35. The computer program as set forth in claim 34,wherein said fault level calculating computer readable program codecomprises a computer readable program code for using the followingconditions: (a) the fault level of each of said output lines is L=1; (b)the fault level of all input lines of a gate is L+1 if the fault levelof the output line of said gate is L; and (c) the fault level of a stemline is the maximum value among L₁, L₂, . . . , Lm if the fault levelsof all fanout branches from said stem are L₁, L₂, . . . , Lm.
 36. Thecomputer program as set forth in claim 32, wherein said fault diagnosistable generating computer readable program code comprises a computerreadable program code for storing a diagnosis value for each fault andeach failing input vector in a two-dimensional table, (Xij)m×n, whoserows correspond to a set of m failing input vectors and the columns to aset of n faults.
 37. The computer program as set forth in claim 32,wherein said multiplet generating computer readable program codecomprises a computer readable program code for finding all or a numberof multiplets from a fault diagnosis table, said multiplet being aminimal set of faults {Fj1, Fj2, . . . , Fjh} such that any failingvector ti in said fault diagnosis table corresponds to at least onenon-zero entry in {Xij1, Xij2, . . . , Xijh} for i=1, 2, . . . , m,wherein (Xij)m×n is said fault diagnosis table whose rows correspond toa set of m failing input vectors and the columns to a set of n faults.38. The computer program as set forth in claim 32, wherein saidmultiplet scoring computer readable program code comprises a computerreadable program code for calculating the score of each obtainedmultiplet, said score of said multiplet being a sum of average diagnosisvalues for all faults in said multiplet, where the average diagnosisvalue of a fault is the average value of all diagnosis values of saidfault for all failing input vectors.
 39. A computer program for modelingphysical defects in an integrated logic circuit by an X-fault model,said X-fault model comprising: a fanout-free X-fault model for eachfanout-free gate, corresponding to any physical defect or defects insaid fanout-free gate or on its output, for which a logic value at theoutput of said fanout-free gate, which is opposite to the fault-freevalue at the output of said gate, is assumed; and a fanout X-fault modelfor each fanout gate, corresponding to any physical defect or defects insaid fanout gate or on its fanout branches, for which different Xsymbols are assumed on the fanout branches of said fanout gate torepresent unknown logic values.
 40. A computer program for carrying outfault simulation for a fanout X-fault of a fanout gate, comprising: acomputer readable program code for X-injecting to assign different Xsymbols to the fanout branches of said fanout gate; a computer readableprogram code for X-propagating to propagate the X symbols to outputs;and a computer readable program code for X-resolving to resolve all Xsymbols at outputs to obtain a final simulation result.
 41. The computerprogram as set forth in claim 40, wherein said X-injecting computerreadable program code comprises a computer readable program code forassigning different X symbols to all the fanout branches of said fanoutgate, each of said X symbols having the form of Xi(bi) where i is asubscript to distinguish said X symbol from all other X symbols and biis a set containing names of said fanout branches to which one of said Xsymbols is assigned.
 42. The computer program as set forth in claim 40,wherein said X-propagating computer readable program code comprises acomputer readable program code for applying a first rule in simulationto preserve inversion information, wherein the inversion of an X symbolis represented by its complement, the logic result of performing an ANDoperation on an X symbol and its complement X symbol is logic 0, and thelogic result of performing an OR operation on an X symbol and itscomplement X symbol is logic
 1. 43. The computer program as set forth inclaim 40, wherein said X-propagating computer readable program codecomprises a computer readable program code for applying a second rule insimulation to preserve branch information, wherein, if the result of alogic function for X symbols, Xi1(b1), Xi2(b2), . . . , Xih(bh), ortheir complements, is neither logic 0 nor logic 1, then a new X symbol,Xj(b1∪b2∪ . . . ∪bh) is used to represent the result, where ∪ representsa set union operation and j is a new subscript that has not been usedyet.
 44. The computer program as set forth in claim 40, wherein saidX-resolving computer readable program code comprises a computer readableprogram code for carrying out 2-valued logic simulation if outputs haveX symbols after X-propagation is done, wherein if outputs of saidintegrated logic circuit have Xi1(b1), Xi2(b2), . . . , Xih(bh), ortheir complements, all logic combinations for branches b1∪b2∪ . . . ∪bhare assigned to said fanout branches and simulated by 2-valuedsimulation one by one.
 45. A computer program for carrying out faultsimulation in an integrated logic circuit including a plurality of inputsignal lines, a plurality of output signal lines, and a plurality ofgates connected between said input signal lines and said output signallines, comprising: a computer readable program code for injectingdifferent symbols into fanout branches of one of said gates inaccordance with circuit information of said integrated logic circuit; acomputer readable program code for simulating said integrated logiccircuit by applying an input vector to the input signal lines of saidintegrated logic circuit to obtain one or more simulated outputresponses at the output signal lines of said integrated logic circuit inaccordance with the circuit information of said integrated logiccircuit, after said different symbols are injected; and a computerreadable program code for identifying a suspicious region of saidintegrated logic circuit where faults are expected to be localized, bycomparing an observed output response obtained at the output signallines of said integrated logic circuit while applying said input vectorto the input signal lines of said integrated logic circuit with saidsimulated output responses.
 46. The computer program as set forth inclaim 45, wherein said simulating computer readable program codecomprises a computer readable program code for propagating said symbolswith number information of said fanout branches to the output signallines of said integrated logic circuit while said input vector isapplied to the input signal lines of said integrated logic circuit, thusobtaining an initial simulated output response at the output signallines of said integrated logic circuit.
 47. The computer program as setforth in claim 45, further comprising a computer readable program codefor calculating a reachable output response from a faulty candidate gateto the output signal lines of said integrated logic circuit inaccordance with the circuit information of said integrated logiccircuit, said identifying means comprising: a computer readable programcode for comparing said observed output response with an expected outputresponse while said input vector is applied; a computer readable programcode for comparing said observed output response with said simulatedoutput responses while said input vector is applied, only when saidobserved output response does not coincide with said expected outputresponse; a computer readable program code for calculating a firstmatching value in accordance with an effective error rate of saidobserved output response and said expected output response within saidreachable output response and a fault level depending upon a substantialdistance between said fault candidate gate and the output signal linesof said integrated logic circuit, when one of said simulated outputresponses coincides with said observed output response; a computerreadable program code for calculating a second matching value of 0, whenone of said simulated output responses does not coincide with saidobserved output response; and a computer readable program code forcalculating a third matching value of an average value of said first andsecond matching values per one of said simulated output responses. 48.The computer program as set forth in claim 47, wherein said firstmatching value is calculated byp(FVEC,G _(i) ,j)=(L(G _(i))/L _(max))·(DEF∩RCO)/|RCO| where FVEC issaid input vector, G_(i) is said fault candidate gate, j is the numberof one of said simulated output responses, RCO is said reachable outputresponse, L(G_(i)) is said fault level under the conditions: 1) thefault level of the output signal lines is L=1, 2) if the fault level ofthe output of a gate is L, the fault level of its input is L+1, and 3)if the fault levels of the fanout signal lines of a gate are L₁, L₂, . .. , the fault level of their stem output is the maximum value of L₁, L₂,. . . , and L_(max) is the maximal fault level within said integratedlogic circuit.
 49. The computer program as set forth in claim 47,wherein said identifying computer readable program code furthercomprises: a computer readable program code for generating a faultdiagnosis table formed by said third matching value in the row of saidinput vector and in the column of said fault candidate gate; a computerreadable program code for renewing said fault diagnosis table byexcluding one or more essential faults from said fault diagnosis tablewhen said essential faults are present therein, each of said essentialfaults being a fault such that an entry in said fault diagnosis table isthe only non-zero entry in the corresponding row and the correspondingcolumn; a computer readable program code for extracting minimal coversfrom said fault diagnosis table, each of said covers being defined by aset of faults such that any failing input vector corresponds to at leastone non-zero entry; and a computer readable program code for generatingmultiplets by adding said essential faults to said minimal covers whenthere are said essential faults in said fault diagnosis table, saidmultiplets being the same as said minimal covers when there are noessential faults in said fault diagnosis table.
 50. The computer programas claim 49, wherein said identifying computer readable program codecomprises a computer readable program code for scoring said multipletsusing average fault diagnosis values per candidate gate.